Programmable Logic & Hardware
by Al Williams

Example 1:

(a)
always @(posedge pb) 
   ready=~ready;

(b)
always @(posedge win0 or negedge ready) 
 begin
   if (ready==0) winner[0]=0; else winner[0]=1;
 end



Listing One
// The following synthesis comments will wrap in print, but of course, should
// be on one line for compilation
// This is the gameshow top-level module
module top1(pb,sw,disp,led,dp);
    input pb;    // host push button
    input [7:0] sw;   // 3-0 are the contestant buttons
    output [6:0] disp;  // A 7 segment display
    output [7:0] led;  // 8 LEDs (not all used)
    output dp;  // decimal point for 7 seg
// These comments have special meaning to the synthesizer and make sure that
// the correct pins get connected to the physical I/O
   // synthesis attribute LOC pb "P10"
   // synthesis attribute LOC led
"P35","P36","P37","P39","P40","P41","P43","P44"
   // synthesis attribute LOC sw
"P70","P66","P71","P72","P5","P11","P7","P6"
   // synthesis attribute LOC disp
"P17","P14","P19","P21","P23","P18","P15"
  // synthesis attribute LOC dp "P24"

 reg ready;    // are we ready?
 wire lock;    // locked out
 wire swready;
 wire ltrig0, ltrig1, ltrig2, ltrig3;  // lock out signals
 wire win0, win1, win2, win3;  // individual win wires
 reg [3:0] winner;  // which is the winner?
 reg [1:0] swin;    //
 reg [3:0] llock;   // locked out?

 initial ready=0;   // for simulation only

 assign led[7]=ready;    // led7 is ready
 assign led[6]=lock;     // led6 means someone won
 assign led[3:0]=winner; // led3-0 tells who won

// if a switch is active and we aren't ready, lock that switch out
 and(ltrig0,sw[0],~ready);
 and(ltrig1,sw[1],~ready);
 and(ltrig2,sw[2],~ready);
 and(ltrig3,sw[3],~ready);

// if a switch is active, no one has won, we are ready, and the
// switch is not locked out, then set the correct win signal
 and(win0,~lock,sw[0],ready,~llock[0]);
 and(win1,~lock,sw[1],ready,~llock[1]);
 and(win2,~lock,sw[2],ready,~llock[2]);
 and(win3,~lock,sw[3],ready,~llock[3]);

// if anyone won, lock everyone out
 or(lock,winner[0],winner[1],winner[2],winner[3]);

// display on 7 segment LED
 show1to4 leddisp(winner,disp);

// if any of the winX wires go high or ready goes low
// we need to set winner[X] correctly
 always @(posedge win0 or negedge ready)
 begin
   if (ready==0) winner[0]=0; else winner[0]=1;
 end
 always @(posedge win1 or negedge ready)
 begin
   if (ready==0) winner[1]=0; else winner[1]=1;
 end
 always @(posedge win2 or negedge ready)
 begin
   if (ready==0) winner[2]=0; else winner[2]=1;
 end
 always @(posedge win3 or negedge ready)
 begin
   if (ready==0) winner[3]=0; else winner[3]=1;
 end

// if ltrigX asserts, or ready goes low we need to set llock[X] correctly
 always @(posedge ltrig0 or negedge ready)
 begin
   if (ltrig0) llock[0]=1; else llock[0]=0;
 end
 always @(posedge ltrig1 or negedge ready)
 begin
   if (ltrig1) llock[1]=1; else llock[1]=0;
 end
 always @(posedge ltrig2 or negedge ready)
 begin
   if (ltrig2) llock[2]=1; else llock[2]=0;
 end
 always @(posedge ltrig3 or negedge ready)
 begin
   if (ltrig3) llock[3]=1; else llock[3]=0;
 end

// when the host presses pb, it toggles the ready state
 always @(posedge pb)
   ready=~ready;

endmodule


Listing Two
// display the number 1 to 4 on the display (other values blank display)
module show1to4(D,O);
    input [3:0] D;
    output [6:0] O;
     reg [6:0] O;
 always
 case (D)
      0:
          O <= 7'b0000000;
       1:
          O <= 7'b0000110;
       2:
          O <= 7'b1011011;
       3:
          O <= 7'b0000000;
       4:
          O <= 7'b1001111;
       5:
          O <= 7'b0000000;
       6:
          O <= 7'b0000000;
       7:
          O <= 7'b0000000;
       8:
            O <= 7'b1100110;
       9:
          O <= 7'b0000000;
      10:
          O <= 7'b0000000;
      11:
          O <= 7'b0000000;
      12:
          O <= 7'b0000000;
      13:
          O <= 7'b0000000;
      14:
          O <= 7'b0000000;
      15:
          O <= 7'b0000000;
endcase

endmodule





